Cadence Automates Wirebonding Design for Stacked-Die Packages; Design Solution Meets Need for Stacked-Die in Growing System-in-Package Market
HDI 2003
SAN JOSE, Calif.--(BUSINESS WIRE)--March 12, 2003--Cadence Design
Systems, Inc. (NYSE:CDN) today announced new capability for designing
stacked-die packages, whose growing popularity is the result of
manufacturers' need to increase functionality in an ever-shrinking
design envelope. Stacked-die packages are particularly common in cell
phones, digital cameras and hand-held devices, which require the
faster turnaround, higher levels of integration and lower costs found
in system-in-package (SiP) solutions.
"Stacked-die packaging is pervasive in the wireless and memory
markets because it facilitates both portability and performance," said
Bret Zahn, vice president of worldwide design and characterization,
ChipPAC Incorporated. "ChipPAC, as the market leader in stacked-die
package design, assembly and test, sees the new Cadence capability as
a way to be more productive and to provide the highest-performance,
most cost-effective design solutions to our customers."
"Using stacked-die packaging allows designers to free up valuable
real estate on both the package and the board," said Charlie
Giorgetti, corporate vice president and general manager of the Cadence
PCB Systems Division. "But, designing an interconnect plan for a stack
of chips is a complicated process. Our new technology is designed to
simplify this process, and help manufacturers get products designed
and in volume production quickly."
Today, virtually all stacked-die packages use wirebonding for the
interconnect to the substrate; a single package design may have
hundreds of wires and multiple-bond patterns for various die
combinations on a single substrate. To address this complexity, the
new wirebonding capability automates the design process and addresses
reliability issues through advanced wire spacing and automated
realignment features. Integrated into the Cadence Advanced Package
Designer Suite, this capability supports all phases of design, from
concept to manufacturing file output. Important features include the
ability to bond as many die as desired; use different spacing rules
for each die and quadrant; and create multiple bonding patterns so
that one substrate can handle multiple-die combinations. Cadence
Advanced Package Designer also provides the capability to combine
flip-chip and wirebond die in same design.
U.S. Pricing and Availability
The stacked-die automated wirebonding capability is part of
Cadence Advanced Package Designer version 15.0, expected to be
available in the second quarter of 2003. The product, which starts at
a U.S. list price of $27,000 for a one-year license, is supported on
Solaris, HP-UX, IBM-AIX platforms, XP Pro, Windows NT and 2000.
Pricing outside of North America is available by contacting a local
Cadence office or distributor.
About Cadence
Cadence is the largest supplier of electronic design technologies,
methodology services, and design services. Cadence solutions are used
to accelerate and manage the design of semiconductors, computer
systems, networking and telecommunications equipment, consumer
electronics, and a variety of other electronics-based products. With
approximately 5,300 employees and 2002 revenues of approximately $1.3
billion, Cadence has sales offices, design centers, and research
facilities around the world. The company is headquartered in San Jose,
Calif., and traded on the New York Stock Exchange under the symbol
CDN. More information about the company, its products and services is
available at www.cadence.com.
Note to Editors: Cadence and the Cadence logo are registered
trademarks of Cadence Design Systems, Inc. All other trademarks are
the property of their respective owners.
CONTACT: Cadence PCB Systems Division
Meg Kenagy, 503/968-4842
mkenagy@cadence.com
